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Freescale Semiconductor Advance Information
Document Number: MC33730 Rev. 6.0, 2/2010
Switch Mode Power Supply with Multiple Linear Regulators
The 33730 is a multiple output power supply integrated circuit for automotive applications. The integrated circuit (IC) incorporates a switching regulator, which operates over a wide input voltage range from 4.5 to 26.5 V. The step-down switching regulator uses a fixed frequency PWM voltage mode control. It has a 3.5 A current limit (typical) and the slewrate is adjustable via a control pin to reduce switching noise. The switching regulator has an adjustable frequency oscillator, which allows the user to optimize its operation over a wide range of input voltages and component values. The linear regulators can be configured either as two normal mode regulators (VDD3, VDDL) and one standby regulator (VKAM), or as one normal mode linear regulator (VDDL) and two standby regulators (VKAM and VDD3 Standby). Two protected outputs [VREF (1, 2)] are used to provide power to external sensors. Features
33730
SWITCHING POWER SUPPLY
EK SUFFIX (PB-FREE) 98ARL10543D 32-LEAD SOICW-EP
* Provides all regulated voltages for Freescale 32-bit ORDERING INFORMATION microcontroller family * Adjustable frequency switching buck regulator with slew-rate Temperature Package Device control Range (TA) * Power sequencing provided MCZ33730EK/R2 - 40C to 125C 32-SOICW-EP * Programmable voltages VDDL, VDD3 - 3% accuracy * Programmable standby regulator VKAM - 15% accuracy, operating down to 4.5 V at the KA_VBAT pin * VDD3 can be programmed as an optional second standby regulator with 15% accuracy * Provides two 5.0 V protected supplies for sensors * Provides reverse battery protection FET gate drive * Provides necessary MCU monitoring and fail-safe support * Pb-free packaging designated by suffix code EK 33730
+ +
VBAT PFD KA_VBAT VIGN IGN_ON
BOOT SW VDDH INV VCOMP VDD3_B VDD3 VDDL_B VDDL VKAM RSTs REGON
+
5.0 V 3.3 V
(32 Bit)
5.0 V
+
VREF1,2 P1 P2 P3 CP GND HRT
MCU
1.5 V KA_1.0 V
5.0V
Figure 1. 33730 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2009 - 2010. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VBAT VBAT UVLO /OVLO Feed Forward Ramp Generator
SW SW Oscillator CP Buck VKAM 15 mA, ILIM, TLIM Control Logic HS Drive Level Shifter FREQ BOOT SR
KA_VBAT VKAM CP PFD REG ON Protection FET Drive Charge Pump
+ -
10.4 K
+ -
Enable
- +
VBG
INV 1.98 K VCOMP
VIGN IGN_ON
VDDH
T-lim VDD3 I
Lim, TLim
VDD3_B
VREF1
5.0 V ILIM=15 0mA 26.5 V,-1V,TLIM ILIM=150 mA 5.0 V
Standby Control Bandgap Preference
VDD3_SBY I Lim, TLim
VDD3
VBG
VDDL I
VREF2
VDDL_B VDDL
26.5 V,-1V,TLIM
P1 P2 P3 RSTKAM RSTH RST3 RSTL Ref. Voltage Programming VKAM, VDDL, VDD3, VDD3_SBY Reference Voltage VKAM Reset Detect VDDH Reset Detect VDD3 Reset Detect VDDL Reset Detect
Lim
Block
HR Timer
HRT GND
Figure 2. 33730 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
HRT RSTKAM RSTH RSTL RST3 VREF2 VDDL VDDH VDDL_B VREF1 REGON IGN_ON VCOMP INV FREQ P1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P3 VIGN GND VDD3_B VDD3 VKAM CP KA_VBAT VBAT VBAT SW SW SR BOOT PFD P2
Note: The exposed pad is electrically and thermally connected to the IC ground.
Figure 3. 33730 Pin Connections Table 1. 33730 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name HRT RSTKAM RSTH RSTL RST3 VREF2 VDDL VDDH VDDL_B VREF1 REGON IGN_ON VCOMP INV FREQ P1 Pin Function Analog Output Open Drain Open Drain Open Drain Open Drain Power Output Analog Input Analog/ Power Input Analog Output Power Output Logic Input Open Drain Analog Output Analog Input Formal Name Definition
Hardware Reset Timer This pin is the hardware reset timer programmed with an external resistor. VKAM Reset VDDH Reset VDDL Reset VDD3 Reset VREF Output 2 VDDL Regulator VDDH Regulator VDDL Regulator Base Drive VREF Output 1 Regulator Hold On VIGN Status Compensation Inverting Input This pin is an open drain reset output, monitoring the VKAM supply to the microprocessor. This pin is an open drain reset output, monitoring the VDDH regulator. This pin is an open drain reset output, monitoring the VDDL regulator. This pin is an open drain reset output, monitoring the VDD3 regulator. This pin is the output of the protected supply VREF2. The pin is supplied from the VDDH through the protection FET. This pin is the VDDL regulator output feedback pin. This pin is the 5.0 V output feedback pin of the buck regulator. The pin is also a power input for the protected outputs VREF1,2. VDDL linear regulator base drive. This pin is the output of the protected supply VREF1. The pin is supplied from the VDDH through the protection FET. Regulator Hold On input pin (5.0 V logic level input). This open drain output signals the status of the VIGN pin. This pin provides switching pre-regulator compensation, it is the output of the error amplifier. Inverting input of the switching regulator error amplifier.
Analog Input Frequency Adjustment Frequency adjustment of the switching regulator. The value of the resistor to ground at this pin determines the oscillator frequency. Logic Input Programming Pin 1 Programming pin 1 for the VDD3, VDDL, and VKAM reference voltages.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PIN CONNECTIONS
Table 1. 33730 Pin Definitions(continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
Pin Number 17 18 19 20 21,22 23,24 25 26 27 28 Pin Name P2 PFD BOOT SR SW VBAT KA_VBAT CP VKAM VDD3 Pin Function Logic Input Analog Output Analog Input Analog Input Power Output Power Input Power Input Analog Output Power Output Formal Name Programming Pin 2 Protection FET Drive Bootstrap Slew-rate Switch Node Battery Voltage Supply Keep Alive Supply Charge Pump Keep Alive Memory Definition Programming pin 2 for the VDD3, VDDL, VKAM reference voltages. Reverse battery protection FET gate drive. This pin is connected to the bootstrap capacitor. Slew-rate Control of the switching regulator. These pins are the source of the internal power switch (N-channel MOSFET). Voltage supply to the IC (external reverse battery protection needed in some applications). This pin is the keep alive supply input. External capacitor reservoir of the internal charge pump. Keep-Alive Memory (standby) supply output. This is a VDD3 regulator output feedback pin. This pin is also the output of the VDD3 standby regulator. 29 30 31 32 VDD3_B GND VIGN P3 Analog Output Ground Analog Input Logic Input VDD3 Linear Regulator Base Drive Ground Voltage Ignition Programming Pin 3 This pin can be used also as an additional standby regulator without the external pass transistor. This pin is a ground. This pin is the ignition switch control input pin. It contains an internal protection diode. Programming pin 3 for the VDD3, VDDL, and VKAM reference voltages.
Analog Input VDD3 Linear Regulator
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings Supply Voltage (VBAT) Keep-Alive Supply Voltage (KA_VBAT) Control Inputs (VIGN, P1, P2, P3), PFD Output Bootstrap Voltage (BOOT, SR) referenced to ground Bootstrap Voltage (BOOT, SR) referenced to SW Charge Pump Output Voltage (CP) Switch Node Voltage SW Sensor Supplies (VREF1, VREF2) Sensor Supplies (VREF1, VREF2) Maximum Slew Rate Regulator Voltages (VDDH,VDD3, VDD3_B, VDDL,VDDL_B, VKAM) Open Drain Outputs (RSTH, RSTL, RST3, RSTKAM, IGN_ON) Regon Input Analog Inputs (VCOMP, INV, FREQ, HRT) ESD Voltage
(1)
Symbol VBAT KA_VBAT
Value - 0.3 to +40 - 18 to +40 - 18 to +40
Unit V V V V V V V V V/s V V V V V
VBOOT VBOOT - VSW VCP VSW VREF VREFMAXSR VREG VDD VREGON VIN VESD
- 0.3 to +50 - 0.3 to +12 - 0.3 to +12 - 2.0 to +40 - 1.0 to +26.5 2.0 - 0.3 to +7.0 - 0.3 to +7.0 -0.3 to +7.0 - 0.3 to + 3.0
Human Body Model - HBM (all pins except BOOT, VDDL, RSTL) Human Body Model - HBM (Pins BOOT, VDDL, RSTL) Machine Model - MM (all pins) Charge Device Model - CDM (all pins) Operational Package Temperature (Ambient Temperature) Storage Temperature Peak Package Reflow Temperature During Maximum Junction Temperature Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Case(5)
(4)
2000 1500 200 750 TA_MAX TSTO - 40 to + 125 - 65 to + 150 Note 3 150 41 1.2 C C C C C/W C/W
Reflow(2), (3)
TPPRT TJ_MAX RJ-A RJ-C
Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), the Machine Model (MM) (AEC-Q100-003), RZAP = 0 ), and the Charge Device Model (CDM), Robotic (AEC-Q100-011). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Thermal resistance measured in accordance with EIA/JESD51-2. Theoretical thermal resistance from the die junction to the exposed pad.
4. 5.
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ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
RECOMMENDED OPERATING CONDITIONS
Table 3. Recommended Operating Conditions All voltages are with respect to ground unless otherwise noted.
Parameter Supply Voltages (VBAT, KA_VBAT) Switching Regulator Output Current (IVDDH) total, VBAT = 6.0 to 26.5 V VDD3 Standby Output Current VKAM Standby Output Current VREF1,2 Output Current Switching Frequency Range * Tracks battery voltage from 6.0 down to 4.5 V. Value *6.0 to 26.5 0 to 2.0 0 to 15 0 to 15 0 to 100 100 to 500 Unit V A mA mA mA kHz
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristic Characteristics noted under conditions 6.0 V KA_VBAT = VBAT 26.5 V, - 40C TA 125C using the typical application circuit, unless otherwise noted.
Characteristic GENERAL Keep-Alive Start-up Voltage (at the KA_VBAT pin), VKAM Output Up Start-up Voltage (at the KA_VBAT pin), VDD3, VDD3 standby, VDDL Up Over-voltage Shutdown Voltage at KA_VBAT pin rising Under-voltage Lock-out Voltage at KA_VBAT pin falling Voltage at KA_VBAT pin rising Under-voltage Lock-out Hysteresis
(6)
Symbol
Min
Typ
Max
Unit
VKAM_STUP VSTUP VSHDN_R VUVLO_F VUVLO_R VUVLO_HYS IQ
4.5 4.5
-- --
-- --
V V V
35
--
42 V
3.6 3.7 --
-- -- 0.1
4.3 4.4 -- A
Sleep Quiescent Current (Sleep mode) VIGN = 0 V, REGON = 0 V, IVKAM = 0 mA, VDD3 OFF, VBAT = 14.0 V, KA_VBAT = 14 V (P1=1, P2=1, P3=1) SWITCHING REGULATOR (VDDH) Buck Converter Output Voltage VBAT = 6.0 to 26.5 V, ILOAD = 100 mA VBAT = 26.5 to 35 V, ILOAD = 100 mA Switching Regulator Current Limit (see Figure 5) Pulse-by-Pulse Current Limit Extreme Current Limit (see Figure 5)(6) SW Drain Source On Resistance(6)
--
--
500
VDDH 4.9 4.85 5.0 5.0 5.1 5.15
V
A ILIM_SW ILIM_SW_EX RDS(ON) -- TSH TSL TSHYS -- 155 1.0 -- -- -- -- 200 195 -- 20 C C -2.25 -3.75 -3.5 -4.5 -4.25 -6.00 m
ID = 500 mA, VBAT = 5.0 V Thermal Shutdown Junction Temperature(6) Thermal Shutdown Hysteresis(6) VDD3 LINEAR REGULATOR VDD3 Output Voltage (Includes Line and Load Regulation) IVDD3 = 0 to -500 mA, See Table 1 for VDD3 Output Settings VDD3 Dropout Voltage (VDDH - VDD3) IVDD3 = -800 mA (VDD3 set to 3.3 V via P1, P2, P3 and with an external transistor) VDD3_B Current Limit, VDD3_B = 0 V, KA_VBAT = 14 V, VBAT = 14 V KA_VBAT = 5.0 V, VBAT = 5.0 V Notes 6. Guaranteed By Design. IVDD3B_Lim VDD3_DO VDD3
% -3.0 -- 3.0 V -- 1.1 1.5 mA -20 -20 -- -- -50 -50
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristic(continued) Characteristics noted under conditions 6.0 V KA_VBAT = VBAT 26.5 V, - 40C TA 125C using the typical application circuit, unless otherwise noted.
Characteristic VDD3 STANDBY LINEAR REGULATOR VDD3 Standby Output Voltage (Includes Line and Load Regulation) IVDD3_SBY = 0 to -15 mA, See Table 1 for VDD3_SBY Output Setting VDD3 Dropout Voltage (KA_VBAT - VDD3) Standby Mode (VDD3 set at 3.3 V via P1, P2, P3) IVDD3 = -10 mA VDD3 Standby Current Limit, VDD3 = 0 V KA_VBAT = 14 V, VBAT = 14 V KA_VBAT = 5.0 V, VBAT = 5.0 V Thermal Shutdown Junction Temperature(7) TSH TSL Thermal Shutdown Hysteresis(7) VDDL LINEAR REGULATOR VDDL Output Voltage (Includes Line and Load Regulation) IVDDL = 0 to -500 mA, See Table 1 for VDDL Output Setting VDDL_B Dropout Voltage (VDDH - VDDL) (VDDL set at 3.3 V via P1, P2, P3) IVDDL = -800 mA VDDL_B Current Limit, VDDL = 0 V KA_VBAT = 14 V, VBAT = 14 V KA_VBAT = 5.0 V, VBAT = 5.0 V VKAM STANDBY LINEAR REGULATOR VKAM Output Voltage (Includes Line and Load Regulation) IVKAM = 0 to -15 mA, See Table 1 for VKAM Output Setting VKAM Dropout Voltage (KA_VBAT - VKAM) IVKAM = -10 mA, VKAM set to 5.0 V (P1 = L, P2 = H, P3 = L) VKAM STANDBY LINEAR REGULATOR (CONTINUED) VKAM Current Limit, VKAM = 0 V KA_VBAT = 14 V, VBAT = 14 V KA_VBAT = 5.0 V, VBAT = 5.0 V Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis(7) Notes 7. Guaranteed By Design.
(7)
Symbol
Min
Typ
Max
Unit
VDD3_SBY -15 VDD3_DO -- IVDD3SBY_LIM -20 -20 -- 150 5.0 -- -- -- -- -- -50 -50 190 -- 20 -- 1.4 -- 15
%
V
mA
C C
TSHYS
VDDL -3.0 VDDL_DO -- -- -- 3.0 280
%
mV
IVDDL_LIM -18 -18 -- -- -50 -50
mA
VKAM -15 VKAM_DO -- -- 1.4 -- 15
%
V
IVKAM_LIM -20 -20 TSH TSL TSHYS -- 150 5.0 -- -- -- -- -- -50 -50 190 -- 20
mA
C C
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristic(continued) Characteristics noted under conditions 6.0 V KA_VBAT = VBAT 26.5 V, - 40C TA 125C using the typical application circuit, unless otherwise noted.
Characteristic SENSOR SUPPLIES VREF1, VREF2 VREF On-resistance, IVREF = -100 mA VREF Current Limit, VREF = -1.0 V
(8) (8)
Symbol
Min
Typ
Max
Unit
RDS(ON) IREF_LIM IREF_REVLIM V(8) IREF_REVLIM TSH TSL TSHYS
-- -150 -- -2.0 -- 150 5.0
-- -280 -- -- -- -- --
500 -450 40 -- 190 -- 20
m mA mA mA C C
VREF Reverse Current Limit, VREF = 26.5 V
VREF Leakage Current, VREF Shut Down, VREF = -1.0 Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis(9) SUPERVISORY AND CONTROL CIRCUITS VIGN Input Voltage Threshold VBAT = 14.0 V, KA_VBAT = 14 V VIGN Hysteresis VIGN Pull-down Current @ 5.0 V VBAT = 14.0 V, KA_VBAT = 14 V REGON Input Voltage Threshold VBAT = 14.0V, Battery Voltage = 14V REGON Input Voltage Threshold Hysteresis REGON Pull-down Current @ 3.0 V Programming Pin Input Voltage Threshold VBAT = KA_VBAT = 14 V Programming P1, P2, P3 Leakage Current @ 14.0 V VDDH Reset Upper Threshold Voltage (VDDH/VDDH) VDDH Reset Lower Threshold Voltage (VDDH/VDDH) VDDL Reset Lower Threshold Voltage (VDDL /VDDL) VDD3 Reset Lower Threshold Voltage (VDD3 /VDD3) VDD3_SBY Reset Lower Threshold Voltage (VDD3_SBY /VDD3_SBY) VKAM Reset Lower Threshold Voltage (VKAM /VkAM)
(9)
VIGN_IH VIGN_IL VIGN-HYS IPD
4.0 2.0 1.7
4.3 2.15 --
4.6 2.4 --
V
V A
10 VIH VIL VIHYS IPD VIH VIL IPD 1.7 -0.3 0.1 5.0 2.5 -0.3 -- 4.0 -3.0 -3.0 -3.0
30 -- -- 0.3 -- -- -- 1.0 8.0 -8.0 -8.0 -8.0
60 -- 1.0 0.4 30 VBAT 1.0 5.0 13.0 -13.0 -13.0 -13.0 A % % % % % V A V V
-3.0 -3.0
-12.5 -12.5
-30 -30 % V
RSTH, RSTL, RST3, RSTKAM Low-level Output Voltage IOL = 5.0 mA IGN_ON Low-level Output Voltage IOL = 5.0 mA -- -- 0.4 -- -- 0.4
V
Notes 8. The short circuit transient events on the VREF outputs must be limited to the voltage levels specified in the Maximum Ratings and slew rates of less than 2.0 V/s, otherwise damage to the part may occur. Refer to the paragraph Sensor Supplies (VREF1, VREF2) on page 17 and typical application circuit diagrams on Figure 8,and Figure 9 for recommended VREF output termination. 9. Guaranteed by design.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V KA_VBAT = VBAT 26.5 V, - 40C TA 125C using the typical application circuit, unless otherwise noted.
Characteristic GENERAL Power On Reset Delay Time (HR Timer) (see Table 7) (Time to RESET up after Regulator in regulation) Power On Reset Delay Time (HR Timer) Accuracy (33 k resistor) Programming Pin Latching Delay SWITCHING REGULATOR Oscillator Frequency (Switching Freq.) Range - Adjustable (Figure 4) Oscillator Frequency Tolerance at 100 kHz (FREQ Pin Open) SW Node Rise Time, VBAT = KA_VBAT = 14 V, ISW = 500 SR pin shorted to SW pin SR pin open SR pin shorted to BOOT pin SW Node Fall Time, VBAT = KA_VBAT = 14 V, ISW = 500 SR pin shorted to SW pin SR pin open SR pin shorted to BOOT pin Notes 10. Guaranteed by design. mA(10) tSW_F -- -- -- 0.83 0.83 0.83 -- -- -- mA(10) Freq fTOL tSW_R -- -- -- 0.96 1.82 2.38 -- -- -- V/ns 100 90 -- -- 500 110 kHz kHz V/ns
(10)
Symbol
Min
Typ
Max
Unit
tD_POR 0 8.0 tLD_P -- -- -- 500 68 12 --
ms
ms s
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33730 multi-output power supply integrated circuit addresses the system power supply needs for applications using the Freescale 32-bit microcontroller family architecture.
FUNCTIONAL PIN DESCRIPTION HARDWARE RESET TIMER (HRT)
This pin is the hardware reset timer input, which provides delays for the Reset outputs. This delay is programmed by an external resistor to GND.
VDDL REGULATOR BASE DRIVE (VDDL_B)
VDDL linear regulator base drive. This output supplies current into the base of the regulator external pass NPN transistor.
VKAM RESET (RSTKAM)
This pin is an open drain reset output monitoring the VKAM supply to the microprocessor. This output is actively pulled low when the VKAM output voltage falls below its reset threshold level.
VREF OUTPUT 1 (VREF1)
This pin is output of the protected supply VREF1. This output supplies sensors outside of the electronic control module and therefore it is protected against short battery and short to -1.0 V. This pin is supplied from the VDDH through the internal protection FET.
VDDH RESET (RSTH)
This pin is an open drain reset output monitoring the VDDH regulator. This output is actively pulled low when the VDDH output voltage falls below its reset lower threshold level or when the VDDH output voltage exceeds its reset upper threshold level
REGULATOR HOLD ON (REGON)
Regulator Hold On input control pin. The 33730 can be enabled or kept in the Normal operational mode by holding this pin high. This is a 5.0 V logic input.
VDDL RESET (RSTL)
This pin is an open drain reset output monitoring the VDDL regulator. This output is actively pulled low when the VDDL output voltage falls below its reset threshold level.
VIGN STATUS (IGN_ON)
This open drain output signals the status of the VIGN pin. This logic output is actively pulled low when the VIGN control input is pulled high.
VDD3 RESET (RST3)
This pin is an open drain reset output monitoring the VDD3 regulator. This output is actively pulled low when the VDD3 output voltage falls below its reset threshold level.
COMPENSATION (VCOMP)
This pin provides switching pre-regulator compensation network. It is the output of the switching regulator error amplifier.
VREF OUTPUT 2 (VREF2)
This pin is output of the protected supply VREF2. This output supplies sensors outside of the electronic control module and therefore it is protected against a battery short and short to -1.0 V. This pin is supplied from the VDDH through the internal protection FET.
INVERTING INPUT (INV)
This pin is the inverting input of the switching regulator error amplifier.
FREQUENCY ADJUSTMENT (FREQ)
This is the frequency adjustment input of the switching regulator. The operating frequency of the switching regulator can be programmed by an external resistor from this pin to ground.
VDDL REGULATOR (VDDL)
This pin is the VDDL regulator output feedback pin. The emitter of VDDL regulator external NPN pass transistor is connected to this pin.
PROGRAMMING PIN 1 (P1)
Programming Pin 1 for the VDD3, VDDL, and VKAM reference voltage. The output voltage of the VDD3, VDDL and VKAM regulators can be programmed by the P1, P2, and P3 pins (see Table 6).
VDDH REGULATOR (VDDH)
This pin is the 5.0 V output feedback pin of the buck regulator. This pin is also a power input for the protected outputs VREF1 and VREF2.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
PROGRAMMING PIN 2 (P2)
Programming Pin 2 for the VDD3, VDDL, and VKAM reference voltage. The output voltage of the VDD3, VDDL and VKAM regulators can be programmed by the P1, P2, and P3 pins (see Table 6).
KEEP ALIVE SUPPLY (KA_VBAT)
This pin is the keep alive supply input. This input is reverse battery protected. This input supplies power to the internal supply and bias circuits that have to do with this VKAM and other always-on supplies.
PROGRAMMING PIN 3 (P3)
Programming Pin 3 for the VDD3, VDDL, and VKAM reference voltages. The output voltage of the VDD3, VDDL and VKAM regulators can be programmed by the P1, P2, and P3 pins (see Table 6).
CHARGE PUMP (CP)
External reservoir capacitor of the internal charge pump. This charge pump provides the voltage needed to sufficiently enhance the gates of the internal n-channel mosfets (VREF1, VREF2, and VDDH) during the low battery condition.
PROTECTION FET DRIVE (PFD)
Reverse battery protection FET gate drive. This pin is an output drive for the gate of the external Reverse Battery Protection N-channel FET.
KEEP ALIVE MEMORY (VKAM)
Keep Alive Memory (standby) supply output. This output supplies power for the module Keep-Alive memory. This output is always on, if the voltage at the KA_VBAT pin is above 4.5 V. VDD3 LINEAR REGULATOR (VDD3) This is a VDD3 regulator output feedback pin.The emitter of VDD3 regulator external NPN pass transitory is connected to this pin. This pin can programmed to be the output of the VDD3 Standby regulator (see Table 6).
BOOTSTRAP (BOOT)
This pin is connected to the bootstrap capacitor. It provides the supply power for the switching regulator highside drive.
SLEW-RATE (SR)
Slew-rate Control of the switching regulator. The slew-rate of the switching regulator can be adjusted by connecting this pin to switch node (SW pin, slow slew-rate selection), BOOT pin (fast slew-rate selection), or it can be left open (medium slew-rate selection).
VDD3 LINEAR REGULATOR BASE DRIVE (VDD3_B)
This pin can be used also as an additional standby regulator without the external pass transistor.This output supplies current into the base of the regulator external pass NPN transistor.
SWITCH NODE (SW)
This pin is the source of the switching regulator internal power switch (N-channel MOSFET source).
GROUND (GND) BATTERY VOLTAGE SUPPLY (VBAT)
Voltage supply to the IC (external reverse battery protection is recommended). This pin is the ground pin of the integrated circuit.
VOLTAGE IGNITION (VIGN)
This pin is the turn-on control input that is controlled through an ignition switch. This pin is reverse battery protected.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33730 - Functional Block Diagram Input Functions
Voltage Programmming Input Protection FET Driver
Output Functions
5 Volt Buck Switching Regulator 5 Volt Protected Outputs (VREF1, VREF2) Linear Regulator Outputs (VDDL, VDD3, VKAM) Ignition Driver
Ignition Input
Internal Functions
Band Gap Reference Oscillator Sleep/Wake Circuitry
Reset Circuitry
5.0 VOLT BUCK REGULATOR
This is the main regulator that supplies 5.0 Volts to the following protected and regulated outputs, VREF1, VREF2, VDD3, and VDDL.
output signal to indicate that the ignition switch has been activated.
VREF1
This output is one of two protected 5.0 volt outputs that can be used to supply external sensors or other analog circuits requiring a regulated, short-circuit protected 5.0 volt supply.
OSCILLATOR
This is the frequency source for the switching (buck) 5 Volt regulator. The frequency of oscillation is selected by an external resistor to ground.
VREF2
This output is one of two protected 5.0 volt outputs that can be used to supply external sensors or other analog circuits requiring a regulated, short-circuit protected 5.0 volt supply.
BAND GAP REFERENCE
This is the main voltage reference, which is used as the standard for all the current and voltage sources in the MC33730.
VDD3 REGULATOR
This is one of three, voltage programmable, regulated supplies. This supply is controlled by the ignition switch.
PROTECTION FET DRIVER
The protection FET is used to prevent reverse battery connections from damaging the MC33730. The gate drive for the Protection FET is provided by this driver circuit.
VDDL REGULATOR
This is one of three, voltage programmable, regulated supplies. This supply is controlled by the ignition switch.
SLEEP/WAKE CIRCUITRY
This circuitry is responsible for the two main modes of operation for the MC33730, Sleep mode and Wake mode. In the Sleep mode, only the keep alive outputs are active, and the rest of the circuitry is in a low power drawing sleep state. In the Wake mode, the MC33730 is fully functional and normal current is being consumed.
VKAM
This is one of three, voltage programmable, regulated supplies. This supply is NOT controlled by the ignition switch.
VOLTAGE PROGRAMMING
P1, P2, and P3 are three logic level inputs that control the voltage that is available on the VDD3, VDDL and VKAM outputs. Table 6 indicates the 8 different combinations of P1, P2, and P3 and the resultant voltage values.
IGNITION DRIVER
This block of circuitry controls all the voltage outputs, except for the keep alive voltage output(s). It also provides an
33730
Analog Integrated Circuit Device Data Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
RESET CIRCUITRY
There are four open drain reset lines that indicate the status of the four voltage outputs; VDDH, VDDL, VDD3, and VKAM. They are labeled: RSTH, RSTL, RST3, and RSTKAM.
REGON INPUT
This input is OR'd with VIGN. However, it is a 5.0 volt logic input, as opposed to VIGN, which is a VBAT level input. This input is controlled by an MCU I/O pin, to hold power up when the ignition switch is turned off, so housekeeping functions can be performed before power is shut off, by lowering the REGON line. IF REGON is not needed, it should be tied to GND.
33730
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATION DESCRIPTION
FUNCTIONAL DEVICE OPERATION
OPERATION DESCRIPTION INTRODUCTION
The 33730 has two supply inputs. The KA_VBAT pin is the supply input for the standby regulators VKAM (and optionally VDD3_SBY, see Table 6) and for the internal supply circuits. The VBAT pin is the power input of the integrated buck regulator, which steps-down the protected battery voltage providing directly the 5.0 V system supply VDDH. VDDH provides power for the main linear regulator(s) VDDL, VDD3, and also for the other module circuits requiring 5.0 V supply voltage (e.g. protected VREF1,2 outputs). If the supply voltage ramps from zero volts up to its nominal level, the 33730 will start at the latest when the supply (battery) voltage reaches VSTUP at the KA_VBAT pin. If the supply voltage ramps down, the 33730 will keep operating (with degradation of the output voltage regulation) down to VUVLO_f at the KA_VBAT pin. The VKAM output stays operational down to VUVLO_f at the KA_VBAT pin. The 33730 will operate in systems with and without standby mode. In the Standby (sleep) mode of operation the IC will draw maximum IQ quiescent current, assuming only the VKAM is used as a standby output, and it is unloaded. When VDD3 is used as an additional standby output the quiescent current increases by approximately another 100 A. Adjustable Switching Frequency The adjustable frequency feature provides the ability to modify the switcher performance for optimized cost (higher frequency, smaller, cheaper components), or higher efficiency and better EMC performance (lower switching frequency for reduced losses and EMI). The operating frequency of the switching regulator can be adjusted by means of an external resistor RF connected from the FREQ pin to ground (see Figure 4).
Frequency vs RFreq 600 Switching Frequency [kHz] 500 400 300 200 100 0 0 20 40 60 80 100 RFreq [kohm ]
POWER UP
The 33730 will safely power up when the power is applied simultaneously (hot plugged) or in the random sequence to the KA_VBAT, VBAT and VIGN (or REGON) inputs.
POWER DOWN
The 33730 will safely power down when the power is disconnected from any of the KA_VBAT, VBAT inputs or when control signals the VIGN or REGON inputs go low.
FSW 18.48 + (5098.7/RFREQ) FSW is the switch frequency in kHz RFREQ is the resistor value in kOhms Figure 4. Switching Regulator Frequency vs. RFreq Value Adjustable Slew-rate The adjustable slew-rate option allows, with selection of the right switching frequency, optimization of the system for EMC performance. Over-voltage Lock-Out (Shutdown) The over-voltage lock-out (shutdown) feature turns the switching regulator off when the input voltage exceeds the VSHDN_r limit. This extends the 33730 capability to survive the severe load dump conditions up to max VBAT. Operation at 100% Duty Cycle The internal charge pump is used to enhance the power MOSFET gate when the switching regulator reaches 100% duty cycle during the low battery conditions. The switching regulator output voltage VDDH is regulated to provide 5.0 V @ 2.0 A with 2% accuracy and it is intended to directly power the digital and analog circuits of the Electronic Control Module (ECM). The switching regulator
UNDERVOLTAGE LOCK-OUT (UVLO)
There is an under-voltage lock-out feature implemented into the IC. When the battery voltage at the KA_VBAT pin falls below VUVLO_f the under-voltage comparator initiates the power down sequence for the whole IC. The under-voltage lock-out circuit has a VUVLO_hys hysteresis and 5.0 s glitch filter in order to prevent spurious tripping its threshold level and consequent system oscillations between the ON and OFF states.
SWITCHING REGULATOR
The 33730 switching regulator is a fixed frequency (externally adjustable) PWM voltage mode controller with integrated low-RDS(ON) N-channel power MOSFET. This architecture is widely flexible and provides a possibility to optimize its operation over a wide range of input voltages. The 33730 switching regulator provide the following features:
33730
Analog Integrated Circuit Device Data Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION OPERATION DESCRIPTION
output current is also used by the following linear regulators VDD3_3, VDDL, and sensor supplies VREF1, and VREF2. The direct voltage conversion to VDDH = 5.0 V together with the Protection FET Driver circuit allows operation of the IC at very low battery voltages, which would otherwise require to use a boost regulator (with an additional system cost) or a different and more expensive switching converter topology (e.g. flyback). Short Circuit Protection The switching regulator is protected against the overcurrent and short-circuit conditions. It integrates a current limit circuit, which has two threshold levels - the pulse by pulse, and the extreme. Pulse by Pulse Current Limit Pulse-by-Pulse Current Limit threshold has a nominal value set ILIM_SW. When the current flowing through switching regulator power FET exceeds this value the power FET is immediately turned off. During the next switching cycle the power FET is turned on again until it is commanded off by its natural duty cycle or until the current reaches the threshold level again. It should be noted that the current limit is blanked for several tens of nanoseconds during the turn-on and turnoff transition times in order to prevent erroneous turn off due to the current spikes caused by switcher parasitic components. Extreme Current Limit. In some cases, during the over-current or short-circuit condition, the inductor current does not sufficiently decay during the off time of the switching period. The current rise during the current limit blanking time is higher than the decay during the off time. In this case the current in the inductor builds up every consecutive switching cycle. In order to prevent the power FET failure during this condition an extreme current limit has been implemented. When the current flowing through the power FET reaches the ILIM_SW_Ext threshold, the switching regulator will shut off for 500 s, before the switching regulator is allowed to turn on again (see Figure 5).
Soft Start The switching regulator has an integrated soft-start feature. During the soft-start sequence the duty cycle of the internal power switch will be gradually increased from low value to the regulation level. This technique prevents any undesirable inrush current into the buck regulator output capacitor.
LINEAR REGULATORS
The 33730 integrates two linear regulator control circuits VDD3 (programmable), VDDL (programmable) both capable of driving up to 15 mA (min.) base current into the external pass NPN transistors. The output voltage of both linear regulators is monitored at their feedback pins (VDD3 and VDDL). If the voltage at any of the VDD3, VDDL feedback pins fall below their regulation level, the supervisory Reset control circuits will assert the corresponding reset signal (RSTL, and/or RST3 lines will be pulled low). See Table 6 for the output voltage selection details. The linear regulators will stay in regulation down to 4.5 V at the KA_VBAT pin. The 33730 linear regulators offer high flexibility and variability of the module design in terms of selectable output voltages as well as wide range of output current capability. There several types of suitable external pass NPN transistors which could be used. The choice of the particular type depends mostly on the expected power dissipation of the pass transistor. The following parts provide good solution and have been bench tested with the 33730: BCP68T1 (SOT-223) NJD2873T4 (DPAK) MJB44H11 (D2PAK) Available from ON Semiconductor. NOTE: The 33730 linear regulators have been designed to use low ESR ceramic output capacitors - see Figure 8 and Figure 9 for the recommended values.
STANDBY REGULATORS
The 33730 integrates two standby linear regulators, the VKAM and the optional standby regulator VDD3 (see Figure 9) for the optional standby circuit).The output voltage levels of both standby linear regulators are programmable and supervised by the Reset control circuits (RSTKAM, and/or RST3). Both the VKAM and VDD3 outputs are capable of delivering IVKAM_LIM and IVDD3_LIM of load current. See Table 6 for the VKAM and VDD3 standby output voltage selection details. The VKAM standby regulator will keep functioning even below VUVLO_f but the specified drop out voltage may not be maintained. NOTE: The 33730 standby regulators have been designed to use low ESR ceramic output capacitors - see Figure 8 and Figure 9 for recommended values.
Ex t. I 4.5A Lim I Lim 3.5A
Inductor Cu rrent
tBLANK 0 TSW
500us d elay
TSW
Switcher FET Gate
Figure 5. 33730 Current Limit
33730
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATION DESCRIPTION
PROGRAMMING LINEAR REGULATOR OUTPUT VOLTAGE
The output voltage of the VDD3, VDDL and VKAM outputs can be externally programmed by placing logic levels on the programming pins P1, P2, and P3 (see Table 6). This extends the application flexibility of the IC without having to use an external resistor divider, thus improving the regulator accuracy over the whole temperature range, and reducing the component count. The status of the programming pin can be selected either by tying the pin to ground (logic level "0"). The logic level "1" can be selected either by tying the programming pin up (the programming pin can be tied up to the battery voltage) or by leaving the pin open. The programming information is read and latched with the 500 s delay after the power is applied to the IC. Table 6. Programming VDD3, VDDL, VKAM Output Voltage
P1
High High High High Low Low Low Low
POWER SEQUENCING (VDDH, VDD3, VDDL)
VDDH, VDD3, and VDDL are power sequenced by means of internal pull-down FETs. During the power up sequence, VDD3 and VDDL will follow VDDH. During the power down sequence the VDD3 and VDDL outputs will be pulled down by the internal pull-down power FETs, and VDDH will be shut off with a defined delay (~100 s typ.). In order to engage the power down sequence, the following conditions have to be met: (VIGN . REGON) + UVLO = Power Down The VDD3 output is not power sequenced when used as a standby regulator.
SENSOR SUPPLIES (VREF1, VREF2)
There are two sensor supplies, VREF1 and VREF2, integrated into the IC. They are internally connected to VDDH through power MOSFETs which protect against short to battery and short to ground conditions. Severe fault conditions on the VREF1 and VREF2 outputs, like shorts to either ground or battery, will not disrupt the operation of the main regulator VDDH, or cause assertion of any Reset signal. IMPORTANT NOTE: The VREF outputs MUST be externally protected against transient voltage events with slew rates faster than 2.0 V/s, otherwise damage to the part may occur. A practical and inexpensive solution consists of using a series RC network connected from the VREF output to ground (see Figures 8 and 9 for typical component values). Other means, such as a single electrolytic capacitor with its capacitance value C > 10 F, may be also used.
P2
High High Low Low High High Low Low
P3
High Low High Low High Low High Low
VDD3
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Standby 2.0 V 2.6 V Standby 2.6 V Standby
VDDL
2.6 V 3.3 V 1.5 V 3.3 V 3.3 V 3.15 V 3.3 V 3.3 V
VKAM
2.6 V 3.3 V 1.0 V 1.0 V 1.0 V 5.0 V 1.0 V 1.5 V
The Programming Pins can be tied high to battery voltage
LOW BATTERY OPERATION
When the battery voltage falls below the specified minimum value, the 33730 switching regulator will enter a 100% duty cycle mode of operation and its output voltage VDDH will follow the decreasing battery voltage. If the battery voltage continues to fall, the VDDH voltage reaches its reset threshold level, and the RSTH signal will be pulled low, but the other linear regulators will continue to operate, and their monitoring signals stay high as long as the VDDH provides sufficient headroom for the regulators to stay in their regulation limits (see Figure 6 and Figure 7). If the battery voltage continues to fall, the linear regulators would not have sufficient headroom to stay in regulation, and their resets would be asserted (RSTL, RST3, or both would be pulled low). At that moment the power down sequence would be engaged. The VKAM standby regulator will operate down to (VKAM and VKAM_DO) and VKAM-DO at the KA_VBAT pin.
PROTECTION FET DRIVE (PFD)
The Protection FET Drive circuit allows using an optional N-channel protection MOSFET (instead of a standard reverse protection diode) to protect against a reverse battery voltage condition. This approach improves the operating capabilities at very low battery voltages. An internal charge pump is used to enhance the Protection FET gate during nominal and low battery conditions. The charge pump will be enabled at the startup voltage. When the battery voltage gets sufficiently high, the Protection FET is turned off and the integrated circuit power input (VBAT pins) are supplied through the body diode of the Protection FET. Use of the Protection FET is not necessary in systems already using a protection diode, relay or when no reverse battery protection is required.
CONTROL INPUT (VIGN)
The VIGN pin is used as a control input to the IC. The regulation circuits will function and draw current from VBAT when VIGN is high (active) or when the REGON pin is high. The VIGN pin has a VIHN-IH power-up threshold VIGN-IL typical
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION OPERATION DESCRIPTION
power-down threshold) and VIGN-HYS (minimum) of hysteresis. VIGN is designed to operate up to max VBAT battery while providing reverse battery and max VBAT load dump protection.
REGON
The REGON feature permits the microcontroller to select a delayed shutdown of the 33730. It holds off the activation of the reset signals to the microcontroller after the VIGN signal has transitioned. This allows the microcontroller to control the power up and power down of the main regulator outputs except for the standby supplies. The REGON pin input threshold voltages allow control by the standard 2.5 V (up to 5.0 V) logic ICs.
The RSTKAM control circuit monitors the VKAM output. If the VKAM output is out of regulation (low), the device will assert the RSTH signal low. All Reset monitoring circuits have a 20 s delay filter to avoid unintended resets caused by noise glitches on the regulator output lines.
HR TIMER
The HR (Hardware Reset) Timer provides the delay between the time when the particular regulator output voltage is in regulation and the release of the Reset signal. This delay can be programmed by a single external resistor. This solution provides better accuracy than the commonly used external RC timer. The HR Timer delay can be programmed in eight 8ms steps from 0 to 56 ms (see Table 7)
.
HARDWARE RESETS (RSTL, RST3, RSTH, and RSTKAM)
The Hardware Resets are open drain, active low outputs capable of sinking 5.0 mA current and able to withstand +7.0 V. The RSTL control circuit monitors the VDDL output. If the VDDL output is out of regulation (low), the device will assert the RSTL signal low. The RST3 control circuit monitors the VDD3 output. If the VDD3 output is out of regulation (low), the device will assert the RST3 signal low. The RSTH control circuit monitors the VDDH output. If the VDDH output is out of regulation (low or high), the device will assert the RSTH signal low.
Table 7. HR Timer Delay Programming
Programming Resistor Value RHRT [ohms] 68 k 33 k 16 k 8.2 k 3.9 k 2.0 k 1.0 k 470 Delay (typ.) [ms] 0 10 19 29 39 48 58 68
VDDH = 5.0 V 4.5V V DDL = VDD3 = 3.3V Battery Voltage
V
KAM
= 1. 0V
POR Delay RSTKAM
RST L, RST 3
POR Delay
RSTH
POR Delay
Figure 6. Battery Voltage Ramp Up
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
VDDH out of regulation B att ery Voltage VDDH = 5. 0 V VDDL = V DD3 = 3. 3V
V DD3, V DDL out of regulat ion 100us
V DDH turned off
VDD3, V DDL act ively pulled low
4.5V 3.0V
V = 1.0V KA M
RS TKA M
RS TL, RS T3
RSTH
Figure 7. Battery Voltage Ramp Down
OPERATIONAL MODES
The 33730 can operate in the two modes: Low quiescent current Sleep mode and Normal mode of operation. Sleep mode, as well as the VKAM regulator. In this case, the IC consumes about 100 A of additional quiescent current (assuming both VKAM and VDD3 Standby outputs are unloaded). NOTE: In the Sleep mode, the RSTKAM and RST3 are not active and their outputs (as well as the outputs of RSTL and RSTH) are in the high-impedance state.
SLEEP MODE
The 33730 operates in the Sleep mode when both the VIGN pin and the REGON pins are pulled low. Both of these pins have internal pull-downs, which assures that the IC is in this defined state when those pins are left open. When the IC enters the Sleep mode, all major functions are disabled except for the Standby regulators. The KeepAlive regulator VKAM stays always operational (see Table 6). If this output stays unloaded, the IC in the Sleep mode consumes very low quiescent current (IQ). If the VDD3 output was programmed as a VDD3 Standby regulator (see Table 6), it too stays operational during the
NORMAL MODE
The 33730 enters the Normal mode of operation when either the VIGN pin or the REGON pin is pulled high. In this case the IC is fully operational with all regulator outputs ready to supply power and all control, monitoring and protection features activated.
33730
Analog Integrated Circuit Device Data Freescale Semiconductor
19
TYPICAL APPLICATIONS OPERATIONAL MODES
TYPICAL APPLICATIONS
Optional Protection FET
Battery 10nF
3.3uH
VBAT VBAT KA_VBAT UVLO /OVLO Feed Forward Ramp Generator
SW Oscillator CP Buck HS Drive, Level Shifter SW FREQ BOOT RFreq
22uH
VDDHDDH = V V = 5.0 5.0V @ 2000 mA(11) @ 2000mA total
100uF
1.0uF
100uF
SS26
1.0uF 1.0 V 10nF 4.7uF
10nF VKAM CP PFD REGON VKAM 15 mA,I Lim, TLim Protection FET Drive CP
Control Logic
SR
Feedback Compensation Network
10.4 k 20k
5.0k 1.98 k
INV
1.5nF
430R
Charge Pump
V BG
20-60 20k 2.2nF
VCOMP VDDH
k(12)
56pF
5.1k
2.2-4.7 F(12)
VIGN IGN_ON Enable VDD3 ILim,TLim VDD3_SBY ILim,TLim V BG 10nF 100nF Q2
5.0 V 1.5R 1.0uF 5.0 V 1.5R 1.0uF 4 x 5.1k
VREF1
5.0 V, ILim=150 mA 26.5V,-1V,TLim 5.0 V, I Lim=150 mA 26.5V,-1V Lim ,T Ref. Voltage Programming Block
T-lim Standby Control Band-Gap Reference
VDD3_B VDD3 4.7uF 10nF
3.3 V
VREF2
VDDL I Lim
VDDL_B
Q1 1.5 V
P1 P2 P3 RSTKAM RSTH RST3 RSTL
VKAM, VDDL, VDD3, VDD3_SBY Ref. Voltage VKAM Reset Detect V DDH Reset Detect VDD3 Reset Detect V DDL Reset Detect
VDDL 10uF HRT HR Timer RHRT 10nF
GND
Recommended Q1, Q2: BCP68T1 (SOT-223) NJD2873T4 (DPAK) MJB44H11 (D2PAK)
Notes 11. The VDDH total current includes the sum of all output currents of the IC. 12. Higher resistance (60 k) and higher capacitance (4.7F) in the compensation network will reduce the VDDH overshoot.
Compensation network values should be optimized for specific circuit applications.
Figure 8. 33730 Typical Application Circuit Table 8. Programming Output Voltage (BOLD denotes selected combinations)
P1 High High High High Low Low Low Low P2 High High Low Low High High Low Low P3 High Low High Low High Low High Low VDD3 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Standby 2.0 V 2.6 V Standby 2.6 V Standby VDDL 2.6 V 3.3 V 1.5 V 3.3 V 3.3 V 3.15 V 3.3 V 3.3 V VKAM 2.6 V 3.3 V 1.0 V 1.0 V 1.0 V 5.0 V 1.0 V 1.5 V
33730
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS OPERATIONAL MODES
Battery 10nF
Optional Protection FET
3.3uH
VBAT VBAT KA_VBAT UVLO /OVLO Feed Forward Ramp Generator
SW Osc illator CP Buck HS Drive, Level Shifter SW FREQ BOOT RFreq
22uH
VDDH = 5.0 5.0V VDDH = V @ 2000 mA(13) @ 2000mA total
1.0uF
100uF
SS26
100uF
1.0uF 1.0 V 10nF 4.7uF
10nF VKAM CP PFD REGON VKAM 15 mA,I Lim, TLim Protection FET Drive CP
Control Logic
SR
Feedback Compens ation Network
10.4 k 20k 1.98 k 5.0k
INV
20-60 20k k(14)
1.5nF
430R
Charge Pump
V BG
2.2nF VCOMP VDDH VDD3 ILim,TLim VDD3_SBY ILim,TLim
56pF
2.2-4.7 F(14)
5.1k
VIGN IGN_ON Enable 10nF 100nF
5.0 V 1.5R 1.0uF 5.0 V 1.5R 1.0uF 4 x 5.1k
VREF1
5.0 V, ILim=150 mA 26.5V,-1V,TLim 5.0 V, I Lim =150 mA 26.5V,-1V,TLim Ref. Voltage Programming Block
T-lim Standby Control Band-Gap Reference V BG
VDD3_B VDD3 3.3 V Standby 4.7uF 10nF Q1 1.5 V VDDL 10uF HRT 10nF
VREF2
VDDL I Lim
VDDL_B
P1 P2 P3 RSTKAM RSTH RST3 RSTL
VKAM, VDDL, VDD3, VDD3_SBY Ref. Voltage VKAM Reset Detect V DDH Reset Detect VDD3 Reset Detect V DDL Reset Detect
HR Timer RHRT
GND
Recommended Q1, Q2: BCP68T1 (SOT-223) NJD2873T4 (DPAK) MJB44H11 (D2PAK)
Notes 13. The VDDH total current includes the sum of all output currents of the IC. 14. Higher resistance (60 k) and higher capacitance (4.7F) in the compensation network will reduce the VDDH overshoot.
Compensation network values should be optimized for specific circuit applications.
Figure 9. 33730 Typical Application, VDD3 Standby Output @ 15 mA Table 9. Programming Output Voltage (BOLD denotes selected combinations)'
P1 High High High High Low Low Low Low P2 High High Low Low High High Low Low P3 High Low High Low High Low High Low VDD3 3.3V 3.3V 3.3V 3.3V 3.3 V Standby 2.0 V 2.6 V Standby 2.6 V Standby VDDL 2.6V 3.3V 1.5V 3.3V 3.3 V 3.15 V 3.3 V 3.3 V VKAM 2.6V 3.3V 1.0V 1.0V 1.0 V 5.0 V 1.0 V 1.5 V
33730
Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10543D listed below.
EK SUFFIX (PB-FREE) 32-PIN SOICW - EP 98ARL10543D REVISION C
33730
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (Continued)
EK SUFFIX (PB-FREE) 32-PIN SOICW - EP 98ARL10543D REVISION C
33730
Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (Continued)
EK SUFFIX (PB-FREE) 32-PIN SOICW - EP 98ARL10543D REVISION C
33730
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 5.0 6.0
DATE 2/2009 2/2010
DESCRIPTION OF CHANGES * * * * * * * * * Initial Release Updated resistors on the INV pin (page 2, 20, 21) Clarified REGON pin operation (page 3, 9, 11, 14) Added sensor supply max. slew rate (page 5,17) Clarified POR delay section with updated typical values (page 10,18) Modified the SW rise and fall time to V/ns (page 10) Provided a switching frequency equation (page 15) Updated the recommended compensation network values (page 20,21) Made format layout corrections
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33730 Rev. 6.0 2/2010

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